FIG. 1 shows a block diagram of components of a display device 10 such as a TFT-LCD (thin film transistor liquid crystal display) device. The display device 10 includes a display panel 12, a source driver block 14, a gate driver 16, a timing controller 18, and a power source 20.
The display panel 12 includes a plurality of source (i.e., data) lines S1, S2, . . . , and so on to SN. The display panel 12 also includes a plurality of gate (i.e., scan) lines G1, G2, . . . , and so on to GM. The display panel 12 further includes an array of N×M pixel electrodes. Each pixel electrode and a corresponding TFT (thin film transistor) are disposed at an intersection of a respective source line and a respective gate line. Each TFT of the display panel 12 has a gate coupled to a corresponding gate line, a source coupled to a corresponding source line, and a drain coupled to a corresponding pixel electrode.
The source driver block 14 includes multiple source drivers for driving the source lines S1, S2, . . . , and SN with display data (DATA) from the timing controller 18. The timing controller 18 also generates a clock signal (CLK), a data initiation signal (DIO), a load signal (LOAD), and a polarity signal (POL), as control signals to the source driver block 14. The CLK signal is used for signal synchronization between the timing controller and the source driver block 14. The DIO signal is used to indicate when the DATA signal has valid RGB color data. The LOAD signal indicates when the source lines S1, S2, . . . , and SN are to be driven with the RGB color data. The POL signal indicates whether the source driver block should perform inversion on the RGB color data.
The power source 20 generates the bias voltages used by the source driver block 14, the gate driver 16, and the display panel in response to control signals from the timing controller 18. The gate driver 16 sequentially drives the gate lines G1, G2, . . . , and GM in response to control signals from the timing controller 18. In this manner, the pixel electrodes of the display panel 12 are driven with the RGB color data at proper timing for displaying images.
The display panel 12 is desired to be larger with advancement of display technology. Thus, the source driver block 14 is comprised of a plurality of source drivers for driving the large number of source lines of a large display panel 12. The signals from the timing controller 18 are routed to such multiple source drivers with much wiring. Such signal transmission through such increased wiring results in increased power consumption and EMI (electromagnetic interference).
FIG. 2 shows example signal routing from the timing controller 18 to the plurality of source drivers including a first source driver 52, a second source driver 54, and a third source driver 56. Such source drivers 52, 54, and 56 are each disposed on a respective film 62, 64, and 66 comprised of a filler material. Such filler material is individually known to one of ordinary skill in the art. The films 62, 64, and 66 are disposed between the display panel 12 and a PCB substrate 72 having the timing controller 18 mounted thereon. Each of the source drivers 52, 54, and 56 drives a respective set of source lines of the display panel 12.
In the example of FIG. 2, the timing controller 18 generates three bits of red color data R[2:0], three bits of green color data G[2:0], and three bits of blue color data B[2:0], via a total of nine wires from the timing controller 18. The timing controller 18 also generates the control signals for the clock signal CLK and the data initiation signal DIO1. The timing controller 18 further generates a reference signal IREF used by the source drivers 52, 54, and 56 when the data signals R[2:0], G[2:0], and B[2:0] are single-ended.
Further in FIG. 2, a GAMMA voltage which is a reference voltage used by a respective DAC (digital to analog converter) within each of the source drivers 52, 54, and 56 is coupled to such source drivers 52, 54, and 56. In addition, at least one POWER voltage is coupled to each of the source drivers 52, 54, and 56.
In the prior art of FIG. 2, each of the signals R[2:0], G[2:0], B[2:0], CLK, DIO1, and IREF are routed to each of the source drivers 52, 54, and 56. In particular, each bit of the RBG data R[2:0], G[2:0], and B[2:0] are routed sequentially in cascade through the source drivers 52, 54, and 56. Thus, nine wires route the nine color bits R[2:0], G[2:0], and B[2:0] from the timing controller 18 to the first source driver 52. Another nine wires route the nine color bits R[2:0], G[2:0], and B[2:0] from the first source driver 52 to the second source driver 54. Furthermore, another nine wires route the nine color bits R[2:0], G[2:0], and B[2:0] from the second source driver 54 to the third source driver 56.
In the prior art, RGB data is transmitted to the source drivers 52, 54, and 56 via the respective nine wires between the timing controller 18 and the first source driver 52 and the respective nine wires between each adjacent pair of the source drivers 52, 54, and 56. Thus in the prior art of FIG. 2, the wiring for the RGB color data is increased for a larger display panel 12 having a larger number of source drivers. Such increased wiring in turn disadvantageously increases power consumption and EMI (electromagnetic interference) during transmission of such RGB color data.
Thus, RGB color data is desired to be transmitted through the multiple source drivers with minimized wiring for large display panels.